zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 86

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

24.0
24.1
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).
24.2
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 53 on page 86.
Notes:
1. A13 must be high for access to data and connection memory positions. A13 must be low to access internal registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mbps.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mbps.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps.
5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps.
(Note 1)
MSB
A13
Memory Address Mappings
Connection Memory Low (CM_L) Bit Assignment
Memory
1
1
1
1
1
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
Bit
15
UA
EN
15
A12
0
0
0
0
0
0
0
0
0
0
0
1
1
.
.
.
.
.
.
.
.
.
.
.
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
V/C
14
Name
UAEN
A11
0
0
0
0
0
0
0
0
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
SSA
13
4
A10
Table 52 - Address Map for Memory Locations (A13 = 1)
0
0
0
0
1
1
1
1
0
1
1
1
1
Stream Address
.
.
.
.
.
.
.
.
.
.
.
SSA
12
3
Conversion between µ-law and A-law Enable
When this bit is low, normal switch without µ-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, switch with µ-law/A-law conversion, and connection
memory high controls the conversion method.
(St0 - 31)
A9
0
0
1
1
0
0
1
1
0
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
SSA
11
2
A8
0
1
0
1
0
1
0
1
0
0
1
0
1
.
.
.
.
.
.
.
.
.
.
.
SSA
10
1
Stream [n]
Stream 14
Stream 15
Stream 30
Stream 31
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
SSA
Zarlink Semiconductor Inc.
.
.
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.
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.
.
.
9
0
ZL50019
SCA
8
7
A7
0
0
0
0
0
0
0
0
0
0
1
1
.
.
.
.
.
.
.
.
.
.
.
.
86
SCA
7
6
A6
0
0
0
0
0
0
0
0
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
Description
SCA
A5
0
0
0
0
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
6
5
A4
0
0
1
1
0
0
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
SCA
5
4
A3
0
0
1
1
0
0
1
1
1
1
1
1
Channel Address
.
.
.
.
.
.
.
.
.
.
.
.
SCA
4
3
(Ch0 - 255)
A2
0
0
1
1
0
0
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
SCA
3
2
A1
0
0
1
1
0
0
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
SCA
A0
0
1
0
1
0
1
0
1
0
1
0
1
2
1
.
.
.
.
.
.
.
.
.
.
.
.
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
.
.
.
.
Ch126
Ch 127 (Note 4)
.
.
.
.
Ch 254
Ch 255 (Note 5)
SCA
1
0
Channel [n]
Data Sheet
CMM
=0
0