zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 88

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note: For proper
2 - 1
Bit
0
15
UA
EN
14
0
Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
PCC1 - 0
CMM = 1
Name
13
0
µ-
law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
12
0
11
Per-Channel Control Bits
These two bits control the corresponding entry’s value on the STio stream.
Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate, per-channel message mode or per-channel BER
mode.
0
MSG
10
7
MSG
9
6
Zarlink Semiconductor Inc.
PC
C1
MSG
0
0
1
1
8
5
ZL50019
MSG
PC
C0
0
1
0
1
88
7
4
MSG
6
3
Description
Channel Output Mode
Per Channel Tristate
BER Test Mode
MSG
Message Mode
5
2
Reserved
MSG
4
1
MSG
3
0
PCC
2
1
PCC
1
0
CMM
Data Sheet
=1
0