zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 9

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

ZL50019
Data Sheet
List of Tables
Table 49 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 50 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 52 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 55 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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