zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 70

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Reset Value: 0000
External Read/Write Address: 004B
15 - 9
1 - 0
External Read Only Address: 004C
Bit
Bit
15
15
0
8
7
0
14
14
0
0
FDM1 - 0
Unused
Name
Name
SLM
LST
H
13
13
Table 36 - Reference Change Control Register (RCCR) Bits (continued)
0
0
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only
Force DPLL Timing Mode
These bits force the DPLL into one of the valid operation modes.
Reserved
In normal functional mode, these bits are zero.
Slew Rate Limiter Status Bit
If the device sets this bit to high, the DPLL phase difference between the input and output
clocks is changing at the slew rate limit defined in the Slew Rate Limit Register (SRLR).
Lock Status Bit
If the device sets this bit to high, while the LDTR and LDIR registers are programmed
properly, the DPLL output clocks are locked to the selected input reference.
If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
12
12
0
0
H
H
11
11
0
0
10
10
0
0
FDM1
0
0
1
1
9
0
9
0
Zarlink Semiconductor Inc.
ZL50019
SLM
FDM0
8
8
0
0
1
0
1
70
LST
MTR
7
7
Description
Description
RFR2
DPLL TIMING Mode
PRS
6
6
1
Automatic
Holdover
Freerun
Normal
RFR1
PRS
5
5
0
RFR0
PMS
4
4
2
RES1
PMS
3
3
1
RES0
PMS
2
2
0
DPM1
Data Sheet
FDM
1
1
1
DPM0
FDM
0
0
0