zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 95

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
Note 1:
Note 2:
10 Data hold from DS rising
12 Acknowledgement hold time.
13 DTA drive high to HiZ
11 Acknowledgement delay time.
1
2
3
4
5
6
7
8
9
CS
DS
R/W
A0-A13
D0-D15
DTA
CS de-asserted time
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
Data setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
From DS low to DTA low:
From DS high to DTA high
Registers
Memory
High impedance is measured by pulling to the appropriate rail with R
A delay of 500 µs to 2 ms (see Section 17.2 on page 46) must be applied before the first microprocessor access is
discharge C
performed after the RESET pin is set high.
Characteristics
L
.
Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access
†
t
CSD
t
DSD
- Motorola Non-Multiplexed Bus Mode - Write Access
Sym.
t
t
t
t
t
t
t
t
t
RWS
RWH
CSD
DSD
t
CSH
t
t
Zarlink Semiconductor Inc.
CSS
t
AKD
AKH
AKZ
AS
DS
AH
DH
t
t
AS
CSS
t
RWS
t
DS
ZL50019
Min.
15
15
10
95
0
5
0
0
0
0
5
4
Typ.
VALID ADDRESS
VALID WRITE DATA
t
AKD
L
, with timing corrected to cancel time taken to
Max.
150
55
12
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
C
(Note 1)
C
C
C
(Note 1)
t
t
t
CSH
AH
RWH
L
L
L
L
L
t
AKH
Test Conditions
= 50 pF
= 50 pF, R
= 50 pF
= 50 pF
= 50 pF, R
t
DH
t
AKZ
Data Sheet
V
V
V
V
V
V
CT
CT
CT
CT
L
L
CT
CT
= 1 K
= 1 K
2