s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 50

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

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Read Configuration Register Command Sequence
synchronous mode. The configuration register can not be changed during device
operations (program, erase, or sector lock).
The configuration register can be read with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be C6h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be read out of the data bus with the address bus set to
address 000h. Once the data has been read from the configuration register, a
software reset command is required to set the device into the correct state.
Read Mode Setting
This setting allows the system to enable or disable burst mode during system op-
erations. Configuration Bit CR15 determines this setting: “1’ for asynchronous
mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock
cycles that must elapse after AVD# is driven active before data will be available.
This value is determined by the input frequency of the device. Configuration Bit
CR13–CR11 determine the setting (see
The wait state command sequence instructs the device to set a particular number
of clock cycles for the initial access in burst mode. The number of wait states that
should be programmed into the device is directly related to the clock frequency.
Figure 1. Synchronous/Asynchronous State Diagram
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
Configuration Register
Synchronous Mode
Set Burst Mode
Command for
(D15 = 0)
A d v a n c e
Asynchronous Read
Synchronous Read
Hardware Reset
Power-up/
Mode Only
Mode Only
Table
Configuration Register
Asynchronous Mode
Set Burst Mode
I n f o r m a t i o n
Command for
(D15 = 1)
13).