s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 93

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s71ws512ne0bfwzz

Manufacturer Part Number
s71ws512ne0bfwzz
Description
Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25
2. Under worst case conditions of 90°C, V
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Parameter
Effective Word Programming Time
Chip Programming Time
Sector Erase Time
Erase Suspend/Erase Resume
utilizing Program Write Buffer
checkerboard data pattern.
Based upon single word programming, not page programming.
erasure.
command. See the
conditions.
Program Suspend/Program
Total 32-Word Buffer
Programming Time
Chip Erase Time
Resume
64 Kword
16 Kword
"Command Definition
(Note 3)
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
VCC
VCC
VCC
ACC
VCC
ACC
VCC
ACC
VCC
ACC
CC
<335.5 (WS256N)
<145.9 (WS256N)
I n f o r m a t i o n
<104 (WS256N)
<86.7(WS256N)
Summary" section for further information on command definitions.
= 1.65 V, 100,000 cycles.
Typ
<0.15
<300
<0.4
<9.4
<64
(Note 1)
<4
<173.4 (WS256N)
<208 (WS256N)
<671 (WS256N)
<292 (WS256N)
Max
<18.8
<600
<128
<20
<20
(Note 2)
2.5
<8
2
°
C, 1.8 V V
Unit
CC
µs
µs
µs
µs
s
s
s
, 10,000 cycles;
Excludes system level
programming prior to
overhead
erasure
Excludes 00h
Comments
(Note 4)
(Note 5)
93

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