s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 88

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Note:
88
Register. The Configuration Register must be set to the Synchronous Read Mode.
Use setup and hold times from conventional program operation.
Addresses
Figure 22. Synchronous Program Operation Timings: CLK Latched Addresses
AVD
CLK
WE#
Data
OE#
CE#
V CC
t AVSC
Addresses
Figure 23. Accelerated Unlock Bypass Programming Timing
AVD#
WE#
Data
OE#
CE#
t AS
ACC
555h
t VC
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
V IL or V IH
t CA
V ID
t CSW
t AVCH
t WP
Program Command Sequence (last two cycles)
t AVDP
1 ms
t AH
A0h
Don't Care
t VID
A d v a n c e
t WC
t VIDS
t WPH
PA
A0h
t D
t DS
PD
I n f o r m a t i o n
Don't Care
t C
PA
PD
VA
t WHWH1
Progress
Read Status Data
In
Don't Care
VA
Complete