hi-3717 QuickLogic Corp, hi-3717 Datasheet

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... BPRZ). The part operates from a single +3.3V supply using only four external capacitors. Each transmit and receive channel has a 32-word by 12-bit FIFO for data buffering. The HI-3717 is available in very small 44-pin 7mm x 7mm Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic packages. ...

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... Interface SI SO ARINC 717 ACLK Clock Divider RSEL HBP Line Receiver RINA 40 KW RINB 40 KW RINA-40 RINB-40 BPRZ Line Receiver HI-3717 VDD HBP Rate Encoder Slew Rate & Loopback Test Control BPRZ Encoder Transmit FIFO Status Register TXFSTAT Control Control Register 0 ...

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... CONVERTER V+ CONVERTER DC/DC converter positive voltage C1+ CONVERTER DC/DC converter fly capacitor for V+ C1- CONVERTER DC/DC converter fly capacitor for V+ Chip +3.3V Supply VDD POWER HI-3717 DESCRIPTION . Data is shifted into SI and out of SO using SCK when HOLT INTEGRATED CIRCUITS 3 Internal Pull-up / Down W 50K W 50K W ...

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... CS FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0 HI-3717 HI-3717 SPI INSTRUCTIONS Instruction op codes are used to read, write and configure the HI-3717. Each SPI read or write operation begins with an 8-bit Host serial instruction. When CS ) pin, pin shift an instruction op code into the decoder, starting with the first rising edge ...

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... The instruction op code is immediately followed by a data byte comprising the 8-bit data word read or written. For a register read or write negated after the data byte is transferred. Table 2 summarizes the HI-3717 SPI instruction set SCK MSB SI ...

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... Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs RXSEL R/W 0 Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input pin. HI-3717 DESCRIPTION TABLE 2. SPI Instruction Set MSB 768 Bits/sec ...

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... No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the receive FIFO. WARNING: In this mode there is no way the HI-3717 can determine frame or sub- frame boundaries. This sync mode overrides all the other sync modes when set to “1”. ...

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... MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word time R/W 0 Not used, Always reads “0” S1:0 R/W 0 Subframe HI-3717 MSB exactly 16 words TABLE ...

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... ARINC 717 data is transmitted between the HI-3717 and host Barker Code microcontroller using the four-wire Serial Peripheral Interface (SPI) ...

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... ARINC 717 requires a basic data rate of 64 wps with support for 128, 256 and 512 wps. The HI-3717 offers an expanded range 8192 wps for testing purposes and future expansion. CTRL0<3>, 32WPS, overrides the state of CTRL0<6:4> and sets the data rate to 32 wps ...

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... Description in Table 7 for register assignment details. Word Count Utility Register, WRDCNT The MATCH pin goes high when the HI-3717 is in the INSYNC condition and the word count and subframe count matches the value programmed in the Word Count Utility Register. Note: The INSYNC pin is set to “ ...

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... INSYNC is set to “0” when the next expected subframe sync mark is missed in the Flight Mode and Software Synchronization Modes. The HI-3717 sync detection logic is reset and the part initiates the full synchronization process again. The data from the subframe preceding the first incorrect subframe sync mark should be discarded ...

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... Receive FIFO is empty reset to “0” when there is at least one word in the Receive FIFO. When the HI-3717 attempts to load a valid word to a full Receive FIF0, the RFOVF flag, RXFSTAT<1>, and the external RFOV pin are set to “1”. The Receive FIFO ignores any attempt to load any additional words full. The RFOVF flag and RFOV pin are reset to “ ...

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... The SPI format for writing an ARINC 717 word and Fast Word to the HI-3717 Transmit FIFO is the same as the read format, except the 12 BIT PARALLEL LOAD SHIFT REGISTER 32 word x 12 bit FIFO ...

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... HI-3717 Line Receiver Input Pins The HI-3717 has two sets of Line Receiver input pins that are shared with the HBP and BPRZ line receivers, RINA/B and RINA/B-40. Only one pair may be used to connect to the ARINC 717 bus. The unused pair must be left floating. The RINA/B pins may be connected directly to the ARINC 717 bus ...

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... HBP DATA BPRZ DATA INSYNC RFIFO (RFEMPTY) RFIFO ( RFFULL ) ROVF 2nd to LAST WORD Bit 10 Bit 11 HBP DATA BPRZ DATA t TEMPTY TEMPTY FIGURE 13. Transmit FIFO Empty Flag Timing HI-3717 t CYC t CES t CES t t SCKR DH MSB FIGURE 10. SPI Serial Input Timing t CYC t DV MSB FIGURE 11 ...

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... FIGURE 15. Bi-Polar Return to Zero (BPRZ) Output Waveforms HARVARD BI-PHASE (HBP) TXHA t TXHB BI-POLAR RETURN ZERO (BPRZ) TXBA t TXBB one level FIGURE 16. Harvard Bi-Phase (HBP) & Bi-Polar Return to Zero (BPRZ) Logic Output Waveforms HI-3717 HBP BIT HBP BIT Data Bit 0 Data Bit 1 +5V + ...

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... Input Voltage: Input Voltage LO Input Current: Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up current ( HI-3717 Power Dissipation at 25°C Plastic Quad Flat Pack ............... 1.5 W, derate 10mW Current Drain per digital input pin ........................... ±10mA Storage Temperature Range ........................ -65°C to +150°C Operating Temperature Range (Industrial): ..... -40°C to +85°C +0 ...

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... LOGIC OUTPUTS (Including TXHA, TXHB, TXBA & TXBB) Output Voltage: Logic "1" Output Voltage Logic "0" Output Voltage Output Current: Output Capacitance: OPERATING VOLTAGE RANGE OPERATING SUPPLY CURRENT Transmitting Data at 8192 words/sec. Transmitting Data in 8192 words/sec. = HI-3717 SYMBOL CONDITIONS HI V 600 ohm load OHH LO V OLH HI ...

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... Line driver transition differential times (Both the Harvard Bi-Phase and Bi-Polar Return to Zero are set to the same slew rate) CNTL0<2:1> CNTL0<2:1> CNTL0<2:1> Transmitter digital outputs transition times Harvard Bi-Phase (HBP) Bi-Polar Return to Zero (BPRZ) HI-3717 + SYMBOL SCK clock period t CYC t ...

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... HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3717PCx uses a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically isolated from the die. ORDERING INFORMATION HI - 3717 PART NUMBER PART NUMBER PART NUMBER HI-3717 To enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad ...

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... REVISION HISTORY P/N Rev Date Description of Change DS3717 NEW 08/11/11 Initial Release DS3717 A 08/23/11 Corrected typographical errors. Deleted QFN power dissipation reference. HI-3717 HOLT INTEGRATED CIRCUITS 22 ...

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... SQ. See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-3717 PACKAGE DIMENSIONS .203 ± .006 (5.15 ± .15) .008 typ (0.2) .394 ± .004 (10.0 ± .10) SQ. .055 .002 ± ...