hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 8

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

REGISTER DESCRIPTIONS (cont.)
15 - 3
4 - 0
7 - 6 RFIFO1:0
4 - 0
The Word Count Utility Register can be programmed to generate an interrupt on the MATCH pin when the data for the specified word
count of the specified subframe is loaded into the Receive FIFO. The Word Count Utility Register can used with any of the standard
ARINC 717 data rate and all of the expanded data rates, except 8192 wps.
1 - 0
Bit
Bit
Bit
7
6
5
5
2
TRANSMIT FIFO STATUS REGISTER: TXFSTAT
FIFO STATUS PIN ASSIGNMENT
REGISTER: FSPIN
WORD COUNT UTILITY REGISTER: WRDCNT
Read: SPI Op-code 0xE8
Write: Read Only
Read: SPI Op-code 0xEA
Write: SPI Op-code 0x6A
Read: SPI Op-code 0xF2
Write: SPI Op-code 0x72
TFEMPTY
TFFULL
TFHALF
TFIFO
Name
Name
Name
C12:0
S1:0
-
-
-
R/W Default Description
R/W Default Description
R/W
R/W
R/W Default Description
R/W
R/W
R/W
R
R
R
R
R
0
0
1
0
0
0
0
0
0
0
Set when the Transmit FIFO contains 32 words
Set when the Transmit FIFO contains
Set when the Transmit FIFO is empty. Reset to “0” when at least one word is loaded to the Transmit
Not used, Always reads “0”
These bits program which Receive FIFO Status Register bit is represented by the RFIFO pin .
The bit programs which Transmit FIFO Status Register bit is represented by the TFIFO pin.
Not used, Always reads “0”
Subframe Word Count - The value is compared to the current word count in the Receive FIFO and
Not used, Always reads “0”
Subframe ID
FIFO.
sets the MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word
time.
00
01
10
11
00
01
10
11
0
1
RFIFO pin is set “1” when Receive FIFO Status Register Bit 2, RFEMPTY, is “1”.
RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
RFIFO pin is set “1” when Receive FIFO Status Register Bit 4, RFFULL, is “1”.
TFIFO pin is set “1” when Transmit FIFO Status Register Bit 7, TTFULL, is “1”.
TFIFO pin is set “1” when Transmit FIFO Status Register Bit 6, TFHALF, is “1”.
Subframe One
Subframe Two
Subframe Three
Subframe Four
HOLT INTEGRATED CIRCUITS
HI-3717
TABLE 6.
TABLE 7.
TABLE 8.
MSB
MSB
MSB
15 14 13 12 11 10 9
X
X
X
7
7
X X
X X
X X X X X X X
8
6
6
5
5
exactly
X X X X X
X X X X X
4
4
3
3
16 words
2
2
1
1
LSB
LSB
0
0
8
X
7
X X X X
6
5
4
3
X
2
X X
1
LSB
0