hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 3

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

PIN DESCRIPTIONS
TXOUTBB
TXOUTBA
TXOUTHB
TXOUTHA
NOCONV
SIGNAL
TEMPTY
RINB-40
RINA-40
INSYNC
MATCH
OUTBB
OUTBA
OUTHB
OUTHA
SYNC0
SYNC1
RFIFO
TFIFO
ROVF
RSEL
ACLK
TXBB
TXBA
TXHB
TXHA
RINB
RINA
GND
SCK
VDD
C2+
C1+
C2-
C1-
MR
SO
CS
V+
SI
V-
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Disables on-chip DC-DC voltage converter
Alternate receiver negative input. Requires external 40K ohm resistor
Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)
Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)
Alternate receiver positive input. Requires external 40K ohm resistor
Chip 0V Supply (All GND pins on package must be connected)
Output is user programmable to indicate the Transmit FIFO Full or Half-full state.
See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.
Output goes high when the transmit FIFO is empty
Output goes high when the receiver is synchronized to the incoming data. Synchroni-
zation occurs at the next valid sync mark following the detection of the proper
number and order of consecutively spaced sync marks. See Table 3.
Output in conjunction with SYNC1 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid when the INSYNC pin is high.
Output in conjunction with SYNC0 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid when the INSYNC pin is high.
Output goes high when the value of the Frame Word Count Register matches the
value in the Frame Count Utility Register, WRDCNT.
Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty
state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.
Receive FIFO Overflow. Output goes high when an attempt is made to load a full
Receive FIFO
Master Reset, active low
Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0
SPI interface serial data input
SPI Clock. Data is shifted into SI and out of SO when
SPI Interface seral data output
Chip Select
Master timing source for receiver and transmitters. 24 MHZ ±0.1%
Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external
32.5 ohm resistor
Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717
bus
Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC
717 bus
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external
32.5 ohm resistor
Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)
Harvard Bi-Phase (HBP) digital low output (external line driver required)
Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5
ohm resistor
Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus
Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus
Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5
ohm resistor
Harvard Bi-Phase (HBP) digital high output (external line driver required)
DC/DC converter negative voltage
DC/DC converter fly capacitor for V-
DC/DC converter fly capacitor for V-
DC/DC converter positive voltage
DC/DC converter fly capacitor for V+
DC/DC converter fly capacitor for V+
Chip +3.3V Supply
. Data is shifted into SI and out of SO using SCK when
HOLT INTEGRATED CIRCUITS
TA B L E 1 .
HI-3717
DESCRIPTION
3
CS
is low.
CS
is low
50K
50K
50K
50K
50K
50K
50K
Pull-up / Down
W
W
W
W
W
Internal
W
W
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up