hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 10

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

FUNCTIONAL DESCRIPTION
OVERVIEW
ARINC 717 is a continuous transmission of 12-bit words in 4 second
frames divided into four 1 second subframes. The programmed
data rate (32 to 8192 wps) determines the number of words per
subframe. The first word of each subframe is reserved for a unique
sync mark. Figure 5 illustrates the relationship between ARINC 717
frames, subframes and words.
The HI-3717 is comprised of independent ARINC 717 receive and
transmit sections easily accessible via a four wire SPI
communications bus. It supports the ARINC 717 Harvard Bi-Phase
(HBP) protocol as well as the Bi-Polar Return to Zero (BPRZ)
auxiliary protocol.
The receiver accepts data from either a Harvard Bi-Phase (HBP) or
a Bi-Polar Return to Zero (BPRZ) bus, recovers the clock, decodes
the data, synchronizes the ARINC 717 data frames using the
unique subframe sync marks and stores the recovered data in a 32
word x 12 bit Receive FIFO.
The ARINC 717 Transmitter accesses data from a 32 word x 12 bit
Transmit FIFO, encodes it into both HBP and BPRZ data streams at
the selected data rate, and converts the digital data stream to
ARINC 717 bus compatible outputs. There are separate outputs for
the HBP and BPRZ ARINC 717 buses.
The receive and transmit sections operate at the same data rate
and they are configured and monitored via the SPI interface.
Refer to Figure 1 for the Block Diagram of the HI-3717
INITIALIZATION AND RESET
The HI-3717 generates a full reset upon application power. The
power-on-reset (POR) sets all registers to their default values,
places the Receive and Transmit FIFOs to their empty state, and
clears the sync detection logic. It also sets both the HBP and BPRZ
outputs to the high impedance state and the input sampling and
decoders are disabled. See Register Descriptions for complete
definition of the default values.
The part can also be initialized to the full reset state by applying a
100ns active low pulse to the external
A software reset is also possible via the SPI communications
interface by writing a “1” to the CTRL1<3>. This bit places both the
Receive and Transmit FIFO’s in the empty state, clears the sync
detection logic, and sets both the HBP and BPRZ line drivers to a
high impedance state.
device is held in the reset state until a “0” is written to CTRL1<3>.
CONFIGURATION
The HI-3717 is configured via the SPI communications bus by
writing to Control Register 0, CTRL0, and Control Register 1,
CTRL1. They are reset to 0x00 following a Power On Reset
(POR) or a Master Reset (
Software Reset, CTRL1<3>, SRST. The function of each register
bit is shown in the Register Descriptions.
All other registers remain unchanged
MR
) but remain unchanged on a
MR
pin.
HOLT INTEGRATED CIRCUITS
. The
HI-3717
10
In order to avoid inadvertent transceiver operation, Control
Register 0, CTRL0, should be programmed last. Writing
CTRL0 sets the desired data rate which, after one bit period,
the internal clocks are enabled. This in turn makes the
transmitter or receiver operational. Changing the data rate on
the fly may result in unpredictable operation during the
transition to the new programmed state. A full reset, POR or
MR
Data Rate
For correct ARINC 717 date rate reception, transmission and bit
timing, the HI-3717 requires a 24 MHz reference clock source
applied to the ACLK input. This clock is divided down to achieve the
data rate programmed with CNTL0<6:4>. The input receive data is
8X oversampled relative to the programmed data rate.
ARINC 717 requires a basic data rate of 64 wps with support for
128, 256 and 512 wps. The HI-3717 offers an expanded range of
32 to 8192 wps for testing purposes and future expansion.
CTRL0<3>, 32WPS, overrides the state of CTRL0<6:4> and sets
the data rate to 32 wps. The required 0.1% timing tolerance is
maintained over all data rates.
Line Driver Output Slew Rates
The slew rate of the HBP and BPRZ outputs is controllable with
CNTR0<2:1>.
ARINC 717 data rates. In addition, a 1.5μs is provided for the
higher data rates and a 10μs for the 32 wps data rate.
Receiver Format
The ARINC 717 format of the receiver is selectable as HBP or
BPRZ by the state in CNTL0<0>, RXSEL, OR’d with the state of the
external RSEL input pin. A “0” on RSEL and CNTL0<0> selects
HBP and a “1” on either RSEL or CNTL0<0> selects BPRZ.
Refer to Table 3 for the detail description of each bit in Control
Register 0.
Input Synchronization Mode
The HI-3717 has three different synchronization modes, depending
on how it is being used.
1. Flight Recorder Mode
, should be issued before reprogramming the data rate.
This is the normal synchronization mode. In this mode the
HI-3717 searches for the four subframe sync marks:
in the correct sequential order starting from SYNC1 and the
exact bit time determined by the programmed word rate. When
synchronization is achieved the INSYNC pin as well as the
INSYNC bit of the Receive FIFO Status Register, RXFSTAT<7>
are set to “1” on the next valid SYNC1 mark. The valid SYNC1
mark and following data words are stored in the Receive FIFO.
Sync time varies from 4 seconds to a worst case of 8 seconds
for a valid data stream.
A 7.5μs slew rate conforms to all the required
SYNC1 = Octal 1107
SYNC2 = Octal 2670
SYNC3 = Octal 5107
SYNC4 = Octal 6670