hi-3717 QuickLogic Corp, hi-3717 Datasheet - Page 4

• Manufacturer Part Number: hi-3717
• Description: Single-rail Arinc 717 Protocol Ic With Spi Interface
• Manufacturer: QuickLogic Corp

SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS
The HI-3717 uses an SPI (Serial Peripheral Interface) for host
access to internal registers and data FIFOs.
communication is enabled through the Chip Select (
and is accessed via a four-wire interface consisting of Serial
Data Input (SI) from the host, Serial Data Output (SO) to the
host and Serial Clock (SCK).
completely self-timed.
The SPI protocol specifies master and slave operation; the
HI-3717 operates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-3717 operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic
communications with the HI-3717 .
As seen in Figure 2, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data as 8-bit bytes.
Once
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on
transfer and re-initializes the HI-3717 SPI for the next transfer.
If
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 2 below.
However the HI-3717 operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-3717 is sending data on SO during
read operations, activity on its SI input is ignored. Figure 3 and
Figure 4 show actual behavior for the HI-3717 SO output.
CS
CS
goes high before a full byte is clocked by SCK, the
is asserted, the next 8 rising edges on SCK latch input
SCK (SPI Mode 0)
SO
CS
SI
must
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
High Z
be set for Mode 0 for proper
All read / write cycles are
MSB
MSB
CS
terminates the serial
HOLT INTEGRATED CIRCUITS
Host serial
CS
) pin,
HI-3717
4
HI-3717 SPI INSTRUCTIONS
Instruction op codes are used to read, write and configure the
HI-3717. Each SPI read or write operation begins with an 8-bit
instruction. When
pin shift an instruction op code into the decoder, starting with
the first rising edge. The op code is shifted into the SI pin, most
significant bit (MSB) first. The SPI can be clocked up to 5 MHz.
The SPI instructions are of a common format. The most
significant bit (MSB) specifies whether the instruction is a write
“0” or read “1” transfer.
For write instructions, the most significant bit of the data word
must immediately follow the instruction op code and is clocked
into its register on the next rising SCK edge. Data word length
varies depending on word type written: 8-bit Control & Status
Register writes, 16-bit Word Count Utility Register writes and
16-bit Transmit FIFO writes.
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the data field bit-length varies with read instruction
type.
Since HI-3717 operates in half-duplex mode, the host discards
the dummy byte it receives while serially transmitting the
instruction op code to the HI-3717.
MSB
SPI INSTRUCTION FORMAT
7
CS
X
6
goes low, the next 8 clocks at the SCK
X
5
X
4
LSB
LSB
X
3
X
2
X
1
X
0
High Z
LSB