ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 48

• Manufacturer Part Number: ppc440gp-3rc500cz
• Description: Power Pc 440gp Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

440GP – Power PC 440GP Embedded Processor
48
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
PCI-X Interface
PCIXAD00:63
PCIXC0:7[BE0:7]
PCIXCap
PCIX133Cap
PCIXClk
PCIXDevSel
PCIXFrame
PCIXGnt0
PCIXGnt1
PCIXGnt2:5
PCIXIDSel
PCIXINT
PCIXIRDY
PCIXM66En
PCIXParHigh
PCIXParLow
PCIXPErr
PCIXReq0
PCIXReq1:5
PCIXReq64
PCIXAck64
PCIXReset
PCIXSErr
PCIXStop
PCIXTRDY
Signal Name
Address/Data bus (bidirectional).
PCI-X Command[Byte Enables]
Capable of PCI-X operation.
PCI-X devices are 133 MHz capable.
Provides timing to the PCI interface for PCI transactions.
Note:
Indicates the driving device has decoded its address as the target
of the current access.
Driven by the current master to indicate beginning and duration of
an access.
Indicates that the specified agent is granted access to the bus.
Indicates that the specified agent is granted access to the bus.
Indicates that the specified agent is granted access to the bus.
Used as a chip select during configuration read and write
transactions.
Level sensitive PCI interrupt.
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
Capable of 66MHz operation.
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].
Reports data parity errors during all PCI transactions except a
Special Cycle.
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
Asserted by the current bus master, indicating a 64-bit transfer.
Indicates the target can transfer data using 64 bits.
Brings PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
Indicates the current target is requesting the master to stop the
current transaction.
I
phase of the transaction.
ndicates the target agent’s ability to complete the current data
If the PCI-X interface is not being used, drive this pin with a
3.3V clock signal at a frequency between 1 and 66MHz
(Sheet 1 of 7)
Description
.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 1.08 – April 3, 2008
O
O
O
O
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
Data Sheet
Notes
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4
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4
4
5
4
5
4
4
4
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4
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AMCC