ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 50

• Manufacturer Part Number: ppc440gp-3rc500cz
• Description: Power Pc 440gp Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

440GP – Power PC 440GP Embedded Processor
50
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
EMCTxEn,
EMC0TxEn
EMCTxErr,
EMC1TxEn
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr00:31
PerWBE0:3
PerBLast
PerCS0:7
PerData00:31
PerOE
PerPar0:3
PerReady
PerR/W
PerWE
Signal Name
MII: Transmit data enabled
RMII 0: Transmit data enabled
MII: Transmit error:
RMII: Transmit data enabled
Used by the PPC440GP to indicate that data transfers have
occurred.
Used by slave peripherals to indicate they are prepared to transfer
data.
End Of Transfer/Terminal Count.
Peripheral address bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerAddr00 is the most significant bit (msb) on this bus.
External peripheral data bus byte enables.
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
External peripheral device select.
Peripheral data bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GP is the
bus master, it enables the selected device to drive the bus.
External peripheral data bus byte parity.
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC440GP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
(Sheet 3 of 7)
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 1.08 – April 3, 2008
O
O
O
O
O
O
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Data Sheet
Notes
1, 5
1, 5
1, 2
1, 4
1, 2
1
2
1
2
1
2
AMCC