ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 75

• Manufacturer Part Number: ppc440gp-3rc500cz
• Description: Power Pc 440gp Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Revision 1.08 – April 3, 2008
DDR SDRAM MemClkOut0 and Read Clock Delay
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
AMCC
Data Sheet
DQS
Data
Package pins
PLB Clock
Cycle
Delay
1/4
D
Stage 1
FF,
XL
C
Q
Programmed
Read Clock
FF Timing:
T
T
T
Delay
IS
IH
P
MemClkOut0(0)
= Propagation delay (D to Q or C to Q) =
Read Clock
= Input setup time = 0.2ns
= Input hold time = 0.1ns
D
PLB Clk
Stage 2
FF
C
Q
T
T
T
T
MD
MD
RD
RD
T
440GP – Power PC 440GP Embedded Processor
T
RD
min =
max =
min =
max =
MD
D
Stage 3
FF
850ps
2600ps
0ps
300ps
C
Q
0.6ns maximum
(SDRAM0_TR1)
Read Select
Mux
ECC
FF: Flip-Flop
XL: Transparent Latch
D
RDSP
FF
C
Q
PLB bus
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