ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 6

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ppc440gp-3rc500cz

Manufacturer Part Number
ppc440gp-3rc500cz
Description
Power Pc 440gp Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
440GP – Power PC 440GP Embedded Processor
6
PPC440GP Functional Block Diagram
The PPC440GP is designed using the IBM
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus
Note: IBM CoreConnect buses provide:
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
• 128-bit PLB interfaces up to 133.33MHz
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
45 internal
13 external
Controller
Universal
Interrupt
32/64-bit data
13-bit addr
133MHz max
Control
DDR SDRAM
Reset
Clock
D-Cache
Controller
32KB
JTAG
Processor Core
PPC440
133MHz max
Timers
MMU
I-Cache
32KB
Trace
Power
Mgmt
Processor Local Bus (PLB)
Bridge
PCI-X
®
Microelectronics Blue Logic
SRAM
8KB
Arb
DCR Bus
DCRs
(4-Channel)
Controller
DMA
Timers
On-chip Peripheral Bus (OPB)
GP
MAL
Architecture.
Bridge
OPB
methodology in which major functional
GPIO
Ethernet
x2
1 MII
or
2 RMII
Revision 1.08 – April 3, 2008
IIC
x2
Controller
External
Bus
UART
x2
66MHz max
32-bit addr
32-bit data
Data Sheet
Bus Master
Controller
External
AMCC

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