ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 74

• Manufacturer Part Number: ppc440gp-3rc500cz
• Description: Power Pc 440gp Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

440GP – Power PC 440GP Embedded Processor
74
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T
Clock delay is set to zero.
I/O Timing—DDR SDRAM T
Notes:
1. T
2. The time values in the table include 1/4 of a cycle at the indicated clock speed.
3. To obtain adjusted T
1/4 of the cycle time for the lower clock frequency (e.g., T
Clock Speed (MHz)
SD
and T
133
133
133
133
133
133
133
133
133
HD
are measured under worst case conditions.
SD
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
and T
Signal Names
HD
values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
SD
and T
MD
) is provided.
Reference Signal
HD
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SD
- 1.875 + 0.25T
RD
) shown below assumes the programmable Read
CYC
T
).
SD
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
(ns)
Revision 1.08 – April 3, 2008
Data Sheet
T
HD
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
(ns)
AMCC