ppc440gp-3rc500cz Applied Micro Circuits Corporation (AMCC), ppc440gp-3rc500cz Datasheet - Page 79

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ppc440gp-3rc500cz

Manufacturer Part Number
ppc440gp-3rc500cz
Description
Power Pc 440gp Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Revision 1.08 – April 3, 2008
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. Again, T
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 3
AMCC
Data Sheet
Read Clock Delayed
Data in Stage 1 D
Data out Stage 1
Data out Stage 3
DQS Stage 1 C
Data in at RDSP
Data out RDSP
Data out Stage 2
Data at pin
DQS at pin
PLB Clock
with ECC
with ECC
with ECC
T
DIN
High
Low
High
Low
High
Low
High
High
Low
Low
T
T
D0
SIN
T
T
P
TE
T
D0
= Propagation delay from Stage 2 input to RDSP input w/o ECC
= Propagation delay from Stage 2 input to RDSP input with ECC
D0
T
D1
P
D1
D0
D1
D2
440GP – Power PC 440GP Embedded Processor
D0
D2
D1
D2
D3
T
TE
D3
D2
D3
D0
D1
D3
D2
(3)
D0
D1
D2
T
D3
D0
D1
= 1.5ns and T
D2
D3
D2
D3
TE
=
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