M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet - Page 19

• Manufacturer Part Number: M25P05-AVDW6G
• Description: 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

M25P05-A
6.1
Table 4.
1. The read identification (RDID) instruction is available only in products with process technology code X and
Write enable (WREN)
The write enable (WREN) instruction
The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase
(SE), bulk erase (BE) and write status register (WRSR) instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
FAST_READ
Instruction
Y (see application note AN1995).
RDID
WREN
WRSR
RDSR
READ
WRDI
RES
DP
PP
SE
BE
(1)
Instruction set
Write enable (WREN) instruction sequence
Write enable
Write disable
Read identification
Read status register
Write status register
Read data bytes
Read data bytes at higher
speed
Page program
Sector erase
Bulk erase
Deep power-down
Release from deep power-
down, and read electronic
signature
Release from deep power-
down
S
C
D
Q
Description
High Impedance
0
(Figure
1
2
One-byte instruction
Instruction
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 0010
1101 1000
1100 0111
1011 1001
0000 1011
1010 1011
7) sets the write enable latch (WEL) bit.
3
4
code
5
6
7
ABh
0Bh
D8h
C7h
B9h
06h
04h
9Fh
05h
01h
03h
02h
Address
AI02281E
bytes
0
0
0
0
0
3
3
3
3
0
0
0
0
Dummy
bytes
0
0
0
0
0
0
1
0
0
0
0
3
0
Instructions
1 to 256
1 to ∞
1 to ∞
1 to ∞
bytes
1 to ∞
1 to 3
Data
0
0
1
0
0
0
0
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