ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 17

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

6 RESET AND CLOCK MANAGEMENT
6.1 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external re-
set at the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
6.1.1 Low Voltage Detector (LVD)
Low voltage reset circuitry generates a reset when
V
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
The Low Voltage Detector can be disabled by set-
ting bit 3 of the option byte.
6.1.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es in the same way as the low voltage reset
ure
Figure 11. Temporization timing diagram after an internal Reset
DD
below V
below V
9).
is:
IT+
IT-
when V
when V
V
Addresses
DD
DD
DD
is falling.
is rising,
V
IT+
Temporization (4096 CPU clock cycles)
(Fig-
$FFFE
6.1.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Figure 9. Low Voltage Detector functional Diagram
Figure 10. Low Voltage Reset Signal Output
Note: Hysteresis (V
V
V
RESET
DD
DD
V
LOW VOLTAGE
WATCHDOG
IT+
DETECTOR
Figure
RESET
FROM
IT+
12, the RESET signal must
-V
IT-
) = V
hys
ST7263B
INTERNAL
RESET
RESET
V
IT-
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