ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 76

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
I²C BUS INTERFACE (Cont’d)
The Acknowledge function may be enabled and
disabled by software.
The I²C interface address and/or general call ad-
dress can be selected by software.
The speed of the I²C interface may be selected be-
tween Standard (0-100 kHz) and Fast I²C (100-
400 kHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 40. I²C Interface Block Diagram
76/132
SDA
SCL
SDAI
SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
The SCL frequency (F
grammable clock divider which depends on the I²C
bus mode.
When the I²C cell is enabled, the SDA and SCL
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistor used depends on the
application.
When the I²C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
OWN ADDRESS REGISTER (OAR)
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
COMPARATOR
INTERRUPT
SCL
) is controlled by a pro-