ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 80

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
I²C BUS INTERFACE (Cont’d)
11.5.5 Low Power Modes
11.5.6 Interrupts
Figure 42. Event Flags and Interrupt Generation
The I²C interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
80/132
Mode
WAIT
HALT
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
*
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.
Description
No effect on I²C interface.
I²C interrupts exit from Wait mode.
I²C registers are frozen.
BERR
ARLO
ADSL
*
BTF
SB
AF
Interrupt Event
ITE
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
STOPF
ADSEL
Event
ARLO
BERR
Flag
BTF
SB
AF
Control
Enable
Bit
ITE
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
Halt
Exit
No
No
No
No
No
No
No