ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 79

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

I²C BUS INTERFACE (Cont’d)
Figure 41. Transfer Sequencing
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
Master Transmitter
Slave Receiver
Slave Transmitter
Master Receiver
S Address
S Address
S
S
EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV5
EV5
Address
Address
A
A
EV1 EV3
EV1
A
A
Data1
EV6
EV6 EV8
Data1
Data1
A
Data1
EV2
A
A
EV3
Data2
EV7
A
Data2
EV8
Data2
A
Data2
EV2
A
A
EV3
EV7
.....
A
EV8
.....
DataN
.....
DataN
.....
DataN
A
DataN
EV2
NA
NA
EV3-1
P
EV7
A
EV4
ST7263B
EV8
P
P
79/132
EV4
P