ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 31

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

I/O PORTS (Cont’d)
9.3.4 Register Description
DATA REGISTERS (PxDR)
Port A Data Register (PADR): 0000h
Port B Data Register (PBDR): 0002h
Port C Data Register (PCDR): 0004h
Read /Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 1111 x000 (FXh)
Note: For Port C, unused bits (7-3) are not acces-
sible.
Bit 7:0 = D[7:0] Data Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
Table 13. I/O Ports Register Map
Address
D7
(Hex.)
7
00
01
02
03
04
05
D6
Register
PADDR
PBDDR
PCDDR
Label
PADR
PBDR
PCDR
D5
D4
MSB
MSB
MSB
MSB
MSB
MSB
D3
7
D2
6
D1
D0
0
5
DATA DIRECTION REGISTER (PxDDR)
Port A Data Direction Register (PADDR): 0001h
Port B Data Direction Register (PBDDR): 0003h
Port C Data Direction Register (PCDDR): 0005h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 1111 x000 (FXh)
Note: For Port C, unused bits (7-3) are not acces-
sible
Bit 7:0 = DD[7:0] Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
DD7
7
4
DD6
DD5
3
DD4
2
DD3
DD2
1
DD1
ST7263B
LSB
LSB
LSB
LSB
LSB
LSB
31/132
0
DD0
0