ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 57

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ST72F63

Manufacturer Part Number
ST72F63
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.3.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
isters:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
Refer to the register descriptions in
11.3.7for the definitions of each bit.
11.3.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
Figure 36. Word Length Programming
Figure
Figure
9-bit Word length (M bit is set)
Start
Bit
8-bit Word length (M bit is reset)
Start
Bit
35).
35. It contains 6 dedicated reg-
Bit0
Bit0
Bit1
Bit1
Break Frame
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Bit2
Bit2
Bit3
Bit3
Section
Bit4
Bit4
Bit5
Bit5
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Bit6
Bit6
Possible
Bit7
Parity
Bit7
Bit
Possible
Parity
Bit8
Bit
Stop
Bit
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
’1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
’1’
Start
Bit
Next Data Frame
Start
Bit
ST7263B
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