ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 84

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
I²C BUS INTERFACE (Cont’d)
I²C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I²C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I²C mode
1: Fast I²C mode
Bits 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I²C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
– Fast mode (FM/SM=1): F
Note: The programmed F
SCL and SDA lines.
I²C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = D7-D0 8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
– Receiver mode: the first data byte is received au-
84/132
FM/SM
matically when the software writes in the DR reg-
ister.
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
D7
7
7
F
F
CC6
SCL
SCL
D6
= f
= f
CC5
D5
CPU
CPU
/(2x([CC6..CC0]+2))
/(3x([CC6..CC0]+2))
CC4
D4
SCL
CC3
D3
SCL
assumes no load on
> 100kHz
SCL
CC2
D2
<= 100kHz
CC1
D1
SCL
CC0
) de-
D0
0
0
I²C OWN ADDRESS REGISTER (OAR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:1 = ADD7-ADD1 Interface address .
These bits define the I²C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
7
0