hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 123

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

5.5
5.5.1
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter WDT and PWM is halted. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous
counter, SCI3-2, SCI3-1, IRQ
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a
maximum is 2/ø (s).
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
108
Subsleep Mode
Transition to Subsleep Mode
Clearing Subsleep Mode
4
to IRQ
0
, WKP
7
to WKP
0
) or by a low input at the RES pin.