hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 204

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
0
0
0
0
1
1
1
1
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register
2. Timer counter C (TCC)
TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode
register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
Bit
Initial value
Read/Write
(IEGR). See 1. IRQ edge select register (IEGR) in 3.3.2 for details. IRQ2 must be set to 1
in port mode register 1 (PMR1) before setting 111 in bits TMC2 to TMC0.
Bit 1
TMC1
0
0
1
1
0
0
1
1
TCC7
R
7
0
Bit 0
TMC0
0
1
0
1
0
1
0
1
TCC6
R
6
0
TCC5
R
5
0
Description
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/64
Internal clock: ø/16
Internal clock: ø/4
Internal clock: øw/4
External event (TMIC): rising or falling edge*
TCC4
R
4
0
TCC3
R
3
0
TCC2
R
2
0
TCC1
R
1
0
(initial value)
TCC0
R
0
0
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