hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 292

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR
bit 7 bit 1
COM CKE1 CKE0 Mode
0
1
0
1
1
3. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
0
1
0
1
1
0
1
SCR3
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
bit 0
0
1
0
0
0
1
1
1
Interrupt Request Conditions
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2 (a).)
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2 (b).)
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure 10.2
(c).)
Asynchronous Internal
mode
Synchronous
mode
Reserved (Do not specify these combinations)
Clock Source SCK
External
Internal
External
I/O port (SCK
Outputs clock with same frequency as bit rate
Outputs clock with frequency 16 times bit rate
Outputs serial clock
Inputs serial clock
Transmit/Receive Clock
3x
Pin Function
Notes
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
3x
pin not used)
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