hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 465

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hd66100

Manufacturer Part Number
hd66100
Description
H8/3867 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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IRR2—Interrupt request register 2
450
Note: * Bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing.
Direct transition interrupt request flag
0 Clearing conditions:
1 Setting conditions:
When IRRDT = 1, it is cleared by writing 0
set to 1, and a direct transition is made
When a SLEEP instruction is executed while DTON is
Bit
Initial value
Read/Write
A/D converter interrupt request flag
0 Clearing conditions:
1 Setting conditions:
When IRRAD = 1, it is cleared by writing 0
When the A/D converter completes conversion and
ADSF is reset
Timer G interrupt request flag
IRRDT
R/(W)*
0 Clearing conditions:
1 Setting conditions:
7
0
the designated signal edge is input
When IRRTG = 1, it is cleared by writing 0
When the TMIG pin is designated for TMIG input and
IRRAD
R/(W)*
6
0
Timer FH interrupt request flag
0 Clearing conditions:
1 Setting conditions:
When IRRTFH = 1, it is cleared by writing 0
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
When counter FH and output compare register FH match
R/W
5
0
Timer FL interrupt request flag
0 Clearing conditions:
1 Setting conditions:
When IRRTFL = 1, it is cleared by writing 0
When counter FL and output compare register FL
match in 8-bit timer mode
IRRTG
R/(W)*
Timer C interrupt request flag
4
0
0 Clearing conditions:
1 Setting conditions:
When IRRTC = 1, it is cleared by writing 0
When the timer C counter value overflows
(from H'FF to H'00) or underflows (from H'00 to H'FF)
IRRTFH
R/(W)*
3
0
Asynchronous event counter interrupt request flag
1 Setting conditions:
0 Clearing conditions:
When IRREC = 1, it is cleared by writing 0
When the asynchronous event counter value overflows
IRRTFL
R/(W)*
2
0
IRRTC
R/(W)*
1
0
IRREC
R/(W)*
H'F7
0
0
System control

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