hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 225

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

4. TCF clear timing
TCF can be cleared by a compare match with OCRF.
5. Timer overflow flag (OVF) set timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare match flag set timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F operation modes
Timer F operation modes are shown in table 9.10.
Table 9.10 Timer F Operation Modes
Operation Mode
TCF
OCRF
TCRF
TCSRF
Note: * When ø
210
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/ø (s). When
the counter is operated in subactive mode, watch mode, or subsleep mode, ø
selected as the internal clock. The counter will not operate if any other internal clock is
selected.
w
/4 is selected as the TCF internal clock in active mode or sleep mode, since the
Reset Active
Reset
Reset
Reset
Reset
Functions Functions Functions/
Functions Held
Functions Held
Functions Held
Sleep
Watch
Halted*
Held
Held
Held
Sub-
active
Functions/
Halted*
Functions Held
Functions Held
Functions Held
Sub-
sleep
Functions/
Halted*
Standby
Halted
Held
Held
Held
w
/4 must be
Module
Standby
Halted
Held
Held
Held