nm34c02 Fairchild Semiconductor, nm34c02 Datasheet - Page 4

• Manufacturer Part Number: nm34c02
• Description: 2k-bit Standard 2-wire Bus Interface
• Manufacturer: Fairchild Semiconductor

NM34C02 Rev. D.2
AC Conditions of Test
Read and Write Cycle Limits (Standard and Low V
Note 3: The write cycle time (t
NM34C02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
Symbol
(Note 3)
t
t
t
t
t
HD:STA
SU:STA
HD:DAT
SU:DAT
SU:STO
t
t
f
t
HIGH
LOW
t
t
t
SCL
BUF
WR
T
t
t
DH
AA
R
F
I
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time - NM34C02
- NM34C02L, NM34C02LZ
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
Parameter
V
10 ns
V
1 TTL Gate and C
CC
CC
x 0.1 to V
x 0.5
IN
CC
x 0.9
L
= 100 pF
Min
250
300
0.3
4.7
4.0
4.7
4.0
4.7
4.7
0
4
100 KHz
Max
100
100
300
3.5
10
15
1
CC
Range 2.7V - 4.5V)
Min
100
0.1
1.3
0.6
1.5
0.6
0.6
0.6
50
0
400 KHz
Max
400
300
0.9
0.3
50
10
15
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Units
KHz
ms
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s