h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 23

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

18A.2 Register Descriptions ....................................................................................................... 585
18A.3 Operation ......................................................................................................................... 593
18A.4 Interrupts.......................................................................................................................... 599
18A.5 Usage Note....................................................................................................................... 601
Section 18B Host Interface
18B.1 Overview.......................................................................................................................... 603
18B.2 Register Descriptions ....................................................................................................... 609
18B.3 Operation ......................................................................................................................... 635
18A.1.3 Input and Output Pins ...................................................................................... 583
18A.1.4 Register Configuration..................................................................................... 584
18A.2.1 System Control Register (SYSCR) .................................................................. 585
18A.2.2 System Control Register 2 (SYSCR2) ............................................................. 586
18A.2.3 Host Interface Control Register (HICR) .......................................................... 588
18A.2.4 Input Data Register (IDR)................................................................................ 590
18A.2.5 Output Data Register (ODR)............................................................................ 590
18A.2.6 Status Register (STR)....................................................................................... 591
18A.2.7 Module Stop Control Register (MSTPCR) ...................................................... 593
18A.3.1 Host Interface Activation ................................................................................. 593
18A.3.2 Control States................................................................................................... 595
18A.3.3 A20 Gate .......................................................................................................... 595
18A.3.4 Host Interface Pin Shutdown Function ............................................................ 597
18A.4.1 IBF1, IBF2, IBF3, IBF4................................................................................... 599
18A.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ............................................ 599
18B.1.1 Features............................................................................................................ 603
18B.1.2 Block Diagram ................................................................................................. 605
18B.1.3 Pin Configuration............................................................................................. 606
18B.1.4 Register Configuration..................................................................................... 607
18B.2.1 System Control Registers (SYSCR, SYSCR2) ................................................ 609
18B.2.2 Host Interface Control Registers 0 and 1 (HICR0, HICR1)............................. 610
18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3)............................. 616
18B.2.4 LPC Channel 3 Address Register (LADR3) .................................................... 619
18B.2.5 Input Data Registers (IDR1 to IDR3) .............................................................. 620
18B.2.6 Output Data Registers (ODR1 to ODR3)......................................................... 621
18B.2.7 Two-Way Data Registers (TWR0 to TWR15)................................................. 622
18B.2.8 Status Registers (STR1 to STR3)..................................................................... 623
18B.2.9 SERIRQ Control Registers (SIRQCR0, SIRQCR1) ........................................ 626
18B.2.10 Module Stop Control Register (MSTPCR) ...................................................... 634
18B.3.1 Host Interface Activation ................................................................................. 635
18B.3.2 LPC I/O Cycles ................................................................................................ 636
LPC Interface (LPC)
................................................................................... 603
Rev. 3.00 Jan 18, 2006 page xxiii of xxviii