h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 678

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 18B Host Interface LPC Interface (LPC)
18B.5 Usage Note
The following points should be noted when using the HIF : LPC.
(1) The host interface provides buffering of asynchronous data from the host processor and slave
(2) Unlike the IDR and ODR registers, the transfer direction is not fixed for the two-way registers
(3) Table 18B.9 shows host address examples for corresponding registers when LADR3 = H'A24F
Rev. 3.00 Jan 18, 2006 page 650 of 1044
REJ09B0280-0300
processor, but an interface protocol that uses the flags in STR must be followed to avoid data
contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
(TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to
TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
and LADR3 = H'3FD0.
No
No
Write 1 to IRQ1E1
ODR1 write
transferred?
OBF1 = 0?
Figure 18B.8 HIRQ Flowchart (Example of Channel 1)
All bytes
Yes
Yes
Slave CPU
SERIRQ IRQ1 output
source clearance
SERIRQ IRQ1
Hardware operation
Software operation
Interrupt initiation
Master CPU
ODR1 read