h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 349

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
11.2.8
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Bit 1
OVF
0
1
Bit 0
CCLRA
0
1
Bit
Initial value
Read/Write
Timer Control Register (TCR)
Description
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
When FRC changes from H'FFFF to H'0000
Description
FRC clearing is disabled
FRC is cleared at compare-match A
IEDGA
R/W
7
0
IEDGB
R/W
6
0
IEDGC
R/W
5
0
IEDGD
R/W
4
0
Rev. 3.00 Jan 18, 2006 page 321 of 1044
BUFEA
R/W
Section 11 16-Bit Free-Running Timer
3
0
BUFEB
R/W
2
0
CKS1
R/W
REJ09B0280-0300
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0