h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 550

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
Bit 3
CLR3
0
1
16.2.9
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at
the end of the bus cycle, and a transition is made to module stop mode. For details, see section
24.5, Module Stop Mode.
Rev. 3.00 Jan 18, 2006 page 522 of 1044
REJ09B0280-0300
Bit
Initial value
Read/Write
Module Stop Control Register (MSTPCR)
Bit 2
CLR2
0
1
—
2
C Bus Interface
MSTP15
R/W
7
0
MSTP14
R/W
6
0
Bit 1
CLR1
—
0
1
—
MSTP13
R/W
5
1
MSTPCRH
MSTP12
R/W
4
1
MSTP11
R/W
3
1
Bit 0
CLR0
—
0
1
0
1
—
MSTP10
R/W
2
1
MSTP9
R/W
1
1
Description
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
MSTP8
R/W
0
1
MSTP7
R/W
7
1
MSTP6
R/W
6
1
MSTP5
R/W
5
1
MSTPCRL
MSTP4
R/W
4
1
MSTP3
R/W
3
1
MSTP2
R/W
2
1
MSTP1
R/W
1
1
MSTP0
R/W
0
1