h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 628

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 18A Host Interface X-Bus Interface (XBS)
Table 18A.10 HIRQ Setting/Clearing Conditions
Host Interrupt
Signal
HIRQ11
(P43)
HIRQ1
(P44)
HIRQ12
(P45)
HIRQ3
(PB0)
HIRQ4
(PB1)
HIRQ Setting/Clearing Contention: If there is contention between a P4DR or PBODR
read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4)
clearing by the host, clearing by the host is held pending during the P4DR or PBODR read/write
by the CPU. P4DR or PBODR clearing is executed after completion of the read/write.
Rev. 3.00 Jan 18, 2006 page 600 of 1044
REJ09B0280-0300
No
No
Figure 18A.3 HIRQ Output Flowchart (Example of Channels 1 and 2)
Write 1 to P4DR
Write to ODR
Setting Condition
Internal CPU reads 0 from bit P43DR, then
writes 1
Internal CPU reads 0 from bit P44DR, then
writes 1
Internal CPU reads 0 from bit P45DR, then
writes 1
Internal CPU reads 0 from bit PB0ODR,
then writes 1
Internal CPU reads 0 from bit PB1ODR,
then writes 1
P4DR = 0?
transferred?
All bytes
Yes
Yes
Slave CPU
HIRQ output high
HIRQ output low
Clearing Condition
Internal CPU writes 0 in bit P43DR, or
host reads output data register 2
Internal CPU writes 0 in bit P44DR, or
host reads output data register 1
Internal CPU writes 0 in bit P45DR, or
host reads output data register 1
Internal CPU writes 0 in bit PB0ODR,
or host reads output data register 3
Internal CPU writes 0 in bit PB1ODR,
or host reads output data register 4
Hardware operations
Software operations
Interrupt initiation
Master CPU
ODR read