STLC5411 ST Microelectronics, STLC5411 Datasheet
STLC5411
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STLC5411 Summary of contents
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... ACTIVATION ONLY” IN NT1 IDENTIFICATION CODE AS STANDARD November 1996 2B1Q U INTERFACE DEVICE ADVANCED ORDERING NUMBER: STLC5411FN ORDERING NUMBER: STLC5411P EASILY INTERFACEABLE WITH ST5451 (HDLC & GCI CONTROLLER), ST5421 SID- GCI TRANSCEIVER AND ANY OTHER GCI, PER GCI IDL or TDM COMPATIBLE DEVICES ...
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... STLC5411 INDEX DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... PIN CONNECTIONS (Top view) PLCC44 MICROWIRE MODE DIP28 MICROWIRE MODE STLC5411 PLCC44 GCI MODE DIP28 GCI MODE 3/72 ...
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... STLC5411 Figure 1: Block Diagram. 4/72 ...
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... NT modes a 15.36 MHz synchronized clock to the rest of the system. Scrambling and descrambling are performed as specified in the US and French specifications. On the system side, STLC5411 can be linked to two bus configuration simply by pin MW bias. MICROWIRE( W/DSI) mode (MWpin = 5V): 144 kbit/s 2B+D basic access data is transferred on a multiplex Digital System Interface with 4 different interface formats (see fig ...
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... STLC5411 PIN FUNCTIONS (no Specific Microwire / GCI Mode) Note: all pin number are referred to Plastic DIP28 package. Pin Name In/Out 1, 4 LO+, LO- Out, Out 2, 3 LI+, LI- In VCCA, VCCD In, In 24, 9 GNDA,GNDD1 In GNDD2 In 10 TSRb Out SCLK Out 20 XTAL2 Out ...
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... Chip Select input: When this pin is pulled low, data can be shifted in and out from the UID through CI & CO pins. When high, this pin inhibits the MICROWIRE interface. For normal read or write operation, CS has to be pulled low for 16 CCLK periods of time. STLC5411 7/72 ...
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... STLC5411 PIN FUNCTIONS (specific GCI mode) Pin Name In/Out 6 FSa In Out 7 FSb Out S0 In TEST2 Out 12 BCLK In Out IO4 In Out TEST1 In 15 IO3 In Out EC Out LFS In 16 IO2 In, Out EC Out ES2 CONF2 In 18 IO1 In Out ES1 ...
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... Configuration input pin. When pulled low, GCI channel assigner is selected (channel number defined by inputs S0, S1, S2). When pulled high, UID is configured by pins CONF1 and CONF2. CMS(cr1 CMS(cr1 CONF1(pin CONF2(pin CONF1(pin CONF1(pin CONF2(pin CONF1(pin STLC5411 Function In/Out FSa Out FSa In FSa Out FSa Out ...
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... STLC5411 MULTIPLE FUNCTION PIN DESCRIPTION Pin 7: S0/FSb/TEST2 Function or In/Out conditions (*) MW(pin MO(pin MW(pin MO(pin (*) Only true if ANATST (internal test signal Pin 10: TSR~/SCLK/TCLK Function or In/Out conditions (*) MW(pin MO(pin MW(pin MO(pin (*) Only true if TDSPANA (internal test signal Pin 12: BCLK Function or In/Out conditions ...
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... TEST1 IO4(cr5 IO4(cr5 Function TDOUT CONF1(pin IO3(cr5 CONF1(pin IO3(cr5 LFS IO3(cr5 IO3(cr5 Function TDIN CONF1(pin ES2 IO2(cr5 CONF1(pin IO2(cr5 CONF1(pin CONF1(pin ES2 IO2(cr5 IO2(cr5 STLC5411 In/Out Out Out Out Out Out In/Out Dr Out Out EC Out Out ...
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... STLC5411 MULTIPLE FUNCTION PIN DESCRIPTION Pin 17: CCLK/S2/CONF2 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 18: CI/IO1/ES1/PLLD [R+] Function or In/Out conditions MW(pin CONF2(pin MO(pin MW(pin CONF2(pin MO(pin Pin 19: CO/S1/CONF1 Function or In/Out conditions MW(pin MO(pin MW(pin MO(pin Pin 22: SFSx/RFS [R+] Function or In/Out conditions NTS(cr2 ...
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... Notes: [R+] = Pull up Resistor : Out OD = Open Drain Output Function ESFR(cr4 SFSr ESFR(cr4 LSD CONF1(pin AIS ESFR(cr4 SFSr CONF1(pin ESFR(cr4 LSD AIS ESFR(cr4 SFSr ESFR(cr4 LSD Function INT MO Function MO STLC5411 In/Out Out OD Out OD In Out OD Out OD In Out OD Out OD In/Out Out OD In In/Out 13/72 ...
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... STLC5411 FUNCTIONAL DESCRIPTION Digital Interfaces STLC5411 provides a choice between two types of digital interface for both control data and (2 B+D) basic access data. These are: a) General Circuit Interface: GCI. b) Microwire/Digital System Interface: W/DSI The device will automatically switch to one of them by sensing the MW input pin at the Power up ...
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... When the D chan- nel port is enabled in TDM mode, D bits are as- signed according to the related format on Dx and Dr . STLC5411 provides a choice of four multiplexed formats for the B and D channels data as shown in fig.2 and 3. Format 1: the 2B+D data transfer is assigned to the first 18 bits of the frame on Br and Bx I/0 pins. ...
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... STLC5411 Bit Clock BCLK determines the data shift rate on the Digital Interface. Depending on mode se- lected, BCLK is an input which may be any multi- ple of 8 kHz from 256 kHz to 6176 kHz or an out- put at a frequency depending on the format and the frequency selected. Possible frequencies are: 256 KHz, 512 KHz, 1536 KHz, Figure 2: DSI Interface formats: MASTER mode ...
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... Figure 3: DSI Interface formats: SLAVE mode. STLC5411 17/72 ...
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... The GCI is a standard interface for the intercon- nection of dedicated ISDN components in the dif- ferent equipments of the subscriber loop : In a Terminal, GCI interlinks the STLC5411, the ISDN layer 2 (LAPD) controller and the voice/data processing components as an audio-processor or a Terminal Adaptor module. ...
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... GCI CHANNEL C Bx/ FSa 8 KHz FSb BCLK MASTER MODE (BCLK = 1.536MHz) GCI CHANNEL SLAVE MODE 4 2 FREE MASTE R MODE STLC5411 GCI CHANNEL C 19/72 ...
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... STLC5411 Figure 4c: GCI multiplex examples, (slave mode). 20/72 ...
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... Configuration NT/TE NT1-AUTO FSb TEST2 IO1 IO1 ES1 IO2 IO2 ES2 IO3 IO3 EC IO4 IO4 TEST1 SFSx SFSx STLC5411 LT-RR-AUTO NT-RR-AUTO TEST2 TEST2 PLDD ES1 EC ES2 LFS LFS TEST1 TEST1 RFS RFS 21/72 ...
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... D7-D0: Register Content Exchange Protocol STLC5411 validates a received byte de- tected two consecutive times identical. (see fig. 5) The exchange protocol is identical for both direc- tions. The sender uses the E bit to indicate that it is sending a Monitor byte while the receiver uses A bit to acknowledge the received byte ...
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... 2nd byte EOM 3r d byte? ? (M2) (or ab ort ack) (X) ack pre -ack ab ort Read y for (M1) (M2) (M2) retr ansmission E & A BITS TIMING STLC5411 X X EOM pre- ack?? Rea dy for (X) a new messag 1st byte (M1) pre -ack (M1) 23/72 ...
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... STLC5411 code is sent permanently by the UID until a new status change occurs in RXACT register. C1 bit is sent first to the line. LINE CODING AND FRAME FORMAT 2B1Q coding rule requires that binary data bits are grouped in pairs so called quats (see Tab.2). Each quat is transmitted as a symbol, the magni- tude of which may be 1 out 4 equally spaced volt- age levels (see Fig ...
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... STLC5411 is frame-synchronized when two consecutive synchwords have been consecutively detected. Frame lock will be maintained until six consecu- tive errored sync-words are detected, which will cause the flywheel to attempt to re-synchronize loss of frame sync condition persists for 480ms ...
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... STLC5411 isters description for details. When NT1-AUTO or NT-RR-AUTO mode is se- lected, bits ps1 and ps2 in M4 channel are con- trolled directly by biasing input pins ES1 and ES2 respectively. e.g. ps1 is sent continuously to the line equal 0 when ES1 input is forced at 0 Volt. Spare M5 and M6 bits ...
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... S/T) aib alarm indication bit (set = 0 to indicate interruption) STLC5411 ...
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... STLC5411 Table 4: NT-to-Network 2B1Q Superframe Technique and Overhead Bit Assignments. FRAMING Quat Positions 1-9 Bit Positions 1-18 Super Basic Frame Frame # # Sync Word 1 1 ISW 2,3,... NT-to-Network superframe delay offset from Network-to-NT superframe by 60 All bits than the Sync Word are scrambled. ...
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... Figure 7: Superframe I/O pin SFS STLC5411 29/72 ...
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... STLC5411 Figure 8: Normalized output pulse form 30/72 ...
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... Figure 9: EOC message processing mode. STLC5411 31/72 ...
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... STLC5411 Figure 10: CRC Errors Processing (auto-mode) 32/72 ...
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... ES1 and ES2 inputs drive the logical values of ps1 and ps2 bits in the M4 channel on the line while EC ouput normally high is driven low using the eoc message ”operate 2B+D loopback. This intends to provide power supply testing command occuring simultaneously with the loopback com- mand. STLC5411 33/72 ...
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... TOR channel). Power on initialization Following the initial STLC5411 enters the power down deactivated state in MICROWIRE mode or in GCI mode de- pending on the polarization of the MW input. All the internal circuits including the master oscil- lator are inactive and in a low power state except for the 10 kHz Tone signal detector ...
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... UID provides the GCI clocks needed for control channel transfer; PUP control in- struction is provided to the UID by pulling low the Bx data input; STLC5411 then reacts sending GCI clocks possible to operate an automatic power up of the UID when a wake up tone is detected from the line by connecting the LSD output directly to the Bx input ...
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... STLC5411 ways to enter quiet mode: QM bit in CR6 register and QM primitive command to write in TXACT register; in this last case, any further primitive will clear quiet mode. AUTOMODE For all auto mode configurations, AIS pin allows a choice of line interface 15mH for the trans- former and resistors line or device side ...
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... RDT EI EI – PDN UAP UAI – – – – – – SP3 AI AI – – – – STLC5411 LT RXACT TXACT (commands) – PUP/DR EIU RES – SP1 – RDT EI FA0 – PDN UAI UAR – – – ...
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... STLC5411 Table 7b: RXACT (indication) and TXACT (command) codes. CODES ...
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... RDT test command forces UID to send data with random equiprobable levels at 80 kbaud. 0100 (FA0): Force act bit to Zero FA0 command forces the act bit the SL3 signal transmitted to the line. Is intended to reflect a transmission failure detected on the network side of the loop relative to UID. STLC5411 39/72 ...
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... W control interface”. Table 8 gives the list of all the STLC5411 internal registers can be used in MICROWIRE mode. Table 9 gives the list of all the STLC5411 internal registers can be used in GCI mode. Registers are grouped by types and address ar- of ...
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... OC0 C2E times identical). If new bits are received at the same time in M4 STLC5411 41/72 ...
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... STLC5411 and M56, both registers RXM4 and RXM56 are queued in the interrupt register stack. Bits act, dea, uoa, sai are dedicated to the activa- tion procedure. Validation is always done in ac- cordance with the ANSI rule: validation at each new activation bit received and confirmed twice independently from the above rules ...
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... In this last case UID returns in the previous state. RR Repetor mode UID activation/deactivation complies with the standard requirements for NT1 or LT equipment depending on NTS bit is select. See state matrix for the detailed behaviour of UID. STLC5411 pursue activation procedure is act bit set to one in the is automatically processed is ...
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... STLC5411 UID activation/deactivation complies with the requirements for repetor equipment. ”LT” or ”NT” behaviour is selected by means of bit NTS. BP1 and BP2 break-points should be set equal one too. See state matrix for the detailed behaviour of UID in this mode of operation. Configuration register 3 (CR3) ...
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... TFB0 = 0: A permanent febe bit = 0 is sent on the line as long as TFB0 = 0 TFB0 = 1: The febe bit sent on the line is normaly computed. RFS Remote febe select. Please report to the figure 10. RFS is usefull in report application to transfert or not the anomalies STLC5411 line does not start the 45/72 ...
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... STLC5411 second line section to the first line section and viceversa. RFS = 1: Transfert anomalies second section first section and viceversa allowed. RFS = 0: Transfert anomalies second section first section and viceversa not allowed. LFS Local febe select. Please report to the figure 10. LFS is usefull in re- ...
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... RXM4 Register is constituted of 8 bits. When the line is fully activated (super frame synchronized), STLC5411 extracts the M4 channel bits. m41 is the act bit; m42 in NT mode is the dea bit m47 is the uoa bit m47 is the sai bit. These bits are under the control of the activation se- quencer ...
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... When the line is fully activated (super frame syn- chronized), STLC5411 extracts the overhead bits. When one of the received spare bits m51, m61, m52 is validated following the criterias selected in the Configuration Register OPR. The RXM56 reg- ister content is queued in the interrupt register stack mask overhead bits is set (see MOB bit in CR4 register) ...
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... TXEOC Register is constituted of 12 bits, 3 bits address (EFG), 1 bit data/message Flag (H), 8 bits information (XEOC1 - XEOC8). When trans- mitting SL2/SL3 or SN3 signal. STLC5411 shall continuously send into the EOC channel field the eoc bits twice per superframe. TXEOC register is loaded in the transmit register at each half a su- perframe ...
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... STLC5411 Table 8: REGISTER ACCESS MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 NOP 0000 000 RESERVED 0001 XXX OPR W 0010 000 OPR R 0010 000 CR1 W 0010 001 CR1 R 0010 001 CR2 W 0010 010 CR2 R 0010 010 CR3 W 0010 011 CR3 R 0010 011 CR4 W 0010 ...
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... XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8 Mode B STLC5411 M45x M46x 0 M48x M61x M52x FEBx FEBx C4x C3x C2x C1x ...
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... STLC5411 Table 9: READ BACK MESSAGES BYTE 1 FUNCTION AD7/4 AD3/1 AD0 OPR 0010 000 1 CR1 0010 001 1 CR2 0010 010 1 CR3 0010 011 1 CR4 0010 100 1 CR5 0010 101 1 CR6 0010 110 TXB1 0011 000 1 TXB2 0011 001 1 RXB1 0011 010 1 RXB2 ...
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... Great care must be taken in the layout of the printed cir- cuit board in order to preserve the high transmis- sion performance of the STLC5411. To maximize performance, do not use the philosophy of separat- ing analog and digital grounds for chip. The 3 GND ...
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... STLC5411 Figure 12: Recommended connections. 54/72 ...
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... Figure 13a: LT Application. STLC5411 55/72 ...
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... STLC5411 Figure 13b: NT Application. 56/72 ...
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... Figure 13c: RR Application. STLC5411 57/72 ...
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... STLC5411 APPENDIX A - STATE MATRIX 58/72 ...
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... STLC5411 59/72 ...
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... STLC5411 APPENDIX B - ELECTRICAL PARAMETERS ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC V Input Voltage IN T Operting Temperature Range A T Storage TemperatureRange stg TRANSMISSION ELECTRICAL PARAMETERS Parameter LINE INTERFACE FEATURES Differential Input Resistance between LI+/LI- (0–20KHz Bandwidth) Common Mode Input Resistance Power up Output Differential Impedance (0–20KHz) between LO+/LO- Power Down Output Diffrential Impedance (0– ...
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... Measured from Measured from 200 25 25 Out First Bit on CO Load = 2LSTTL Loads Load = 80pF + 2LSTTL Loads STLC5411 Typ. Max. Unit MHz +100 ppm 50 ns pk- 4095 KHz 6144 KHz ns ns ...
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... STLC5411 Figure 14: BCLK, FSA, FSB, SLAVE MODE, DELAYED MODE, FORMATS (MW ONLY). Figure 15: BCLK, FSA, FSB, SLAVE MODE, NON DELAYED MODE, FORMATS (MW ONLY). 62/72 ...
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... THE FRAME Note 1: in accordance to the selected frequency. High level duration - Low level duration t t DBF DBF t SECOND BIT SEVENTH BIT FIRST BIT OF OF THE OF THE THE FRAME FRAME FRAME STLC5411 DBF DBF DBF DBF EIGHT BIT OF THE FRAME D96TL253 63/72 ...
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... STLC5411 Figure 18: BCLK, FSA, FSB, MASTER MODE, NON DELAYED MODE, FORMATS 1 3 (MW ONLY). Figure 19: BCLK, FSA, FSB, MASTER MODE, FORMAT 4 ALWAYS NON DELAYED MODE, (MW AND GCI MODE). 64/72 ...
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... Figure 20: BX, DX, BR, DR, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS (MW ONLY) Figure 21: BX, DX, BR, DR, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED, (MW & GCI MODE) STLC5411 65/72 ...
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... STLC5411 Figure 22: SPECIAL CASE BR, DR, ONLY FIRST BIT OF THE FRAME, IN SLAVE AND NON DE- LAYED MODES FORMATS 1 3 (MW MODE), FORMAT 4 (MW & GCI MODE) Figure 23: TSRB, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS (MW ONLY) 66/72 ...
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... Figure 24: TSRB, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED MODE (MW & GCI) Figure 25: SPECIAL CASE TSRB FIRST CHANNEL OF THE FRAME, IN SLAVE & NON DELAYED MODE, FORMATS 1 3 (MW MODE), FORMAT 4 (MW & GCI MODE) STLC5411 67/72 ...
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... STLC5411 Figure 26: DCLK, DX CONTINUOUS MODE SLAVE & MASTER, DELAYED & NON DELAYED MODES ALL FORMATS IN MW MODE ONLY Figure 24: MCLK ALL MODES Figure 25: MW PORT Mode A 68/72 ...
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... Figure 26: MW PORT Mode B STLC5411 69/72 ...
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... STLC5411 PLCC44 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 17.4 B 16.51 C 3.65 D 4.2 d1 2.59 d2 0.68 E 14.99 e 1.27 e3 12.7 F 0. 1.16 M1 1.14 70/72 mm MAX. MIN. 17.65 0.685 16.65 0.650 3.7 0.144 4.57 0.165 2.74 0.102 16 0.590 0.101 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108 0.027 0.630 0.050 0.500 0.018 0.028 0.004 0.046 0.045 ...
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... DIP28 PLASTIC PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 33. 4.445 L mm MAX. MIN. 0.31 0.009 37.34 16.68 0.598 14.1 3.3 STLC5411 inch TYP. MAX. 0.025 0.018 0.012 0.050 1.470 0.657 0.100 1.300 0.555 0.175 0.130 71/72 ...
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... STLC5411 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice ...