STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 21

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

Data is transmitted in both directions at half the
data clock rate. The information is clocked by the
transmitter on the front edge of the data clock and
can be accepted by the receiver after 1 to 1.5 pe-
riod of the data clock.
The data clock (BCLK) is a square wave signal at
twice the data transmission frequency on Bx and
Br with a 1 to 1 duty cycle. The frequency can be
choosen from 512
modularity. Data transmission rate depends only
on the data clock rate.
Table 1: GCI Configuration selection.
* Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode.
When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is
automatically selected
When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected.
* * Connected to V
Pin Number
28
27
19
17
18
16
15
14
22
7
S0/FSb/TEST2
IO4/TEST1
S1/CONF1
S2/CONF2
SFSx/RFS
Pin name
CC
IO1/ES1
IO2/ES2
IO3/EC
MW
M0
through internal pull-up resistors.
to 6176 kHz with 16 kHz
LT/NT12*
SFSx
IO1
IO2
IO3
IO4
S1
S2
S0
0
0
NT/TE
SFSx
FSb
IO1
IO2
IO3
IO4
0
1
0
1
The Frame Clock FSa is a 8 kHz signal for syn-
chronization of data transmission. The front edge
of this signal gives the time reference of the first
bit in the first GCI input and output channel, and
reset the slot counter at the start of each frame
When some GCI channels are not selected on
devices connected to the same GCI link, these
time slots are free for alternative uses.
GCI configuration selection is done by biasing of
input pins MW, M0, CONF1, CONF2 according to
TABLE1.
Configuration
NT1-AUTO
TEST2
TEST1
SFSx
ES1
ES2
EC
0
1
1
1
LT-RR-AUTO
TEST2
TEST1
PLDD
RFS
LFS
EC
0
1
1
0
NT-RR-AUTO
STLC5411
TEST2
TEST1
RFS
ES1
ES2
LFS
0
1
0
0
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