STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 40

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

STLC5411
0101 (PDN): Power Down
PDN command forces UID to power down state. It
should normally be used after UID has been set
in a known deactivated state, e.g. in an LT after a
DI status indication has been reported. In GCI, C/I
indication DI is sent twice on Br output before UID
powers down.
0110 (UAR): U-interface-only Activation Request
Being Power Up and deactivated , UAR com-
mand forces UID through the appropriate se-
quence to activate the loop without activating the
S/T interface. SL2/SL3 signal is sent with uoa bit
set to zero. With the line already active, UAR
command forces bit uoa equal zero: this is in-
tended to deactivate the S/T interface.
0111 (QM): Quiet Mode
This command has the same effect as in NT
mode.
1000 (AR): Activation Request
Being Power Up and deactivated, AR instruction
forces UID through the appropriate sequence to
activate the line by sending TL followed by SL1.
SL2/SL3 signal is sent with uoa bit equal one.
Beeing in the U-only-active states, AR command
forces the uoa bit equal 1 to the line. Is intended
to activate the S/T interface.
1010 (ARL): Activation Request with Loopback
ARL test command forces UID through the appro-
priate sequence to activate with the complete
transmit data stream looped-back to the receiver.
When this loop-back is disabled by DR command,
UID is ready to operate a warm start if a new ARL
command is issued.
1011 (SP3): Send Single Pulse +3, -3
SP3 test command forces UID to send +3, -3
pulses to the line, one pulse per frame.
1100 (AI): Activation Indicate
AI is an optional command recognized only when
BP2 bit in CR2 register is set equal one or LT-
RR-AUTO mode is selected. Beeing in the super-
frame-synchronized state with act bit received
from the line equal one, AI command allows UID
to send act bit equal one to the line.
1111 (DI): Deactivation Indicate
The DI command allows the UID to automatically
enter the power down state if the line is deacti-
vated. DI command has no effect as long as the
line is not deactivated (DI status indication re-
ported).
LT mode: Status indication
0001 (EIU): Error Indication Interface U
EIU status indication reports an error at U inter-
face. It can be a ‘loss at signal‘ a ‘loss of
sync‘,‘expiry of Timer 4 lias reset UID for cold-
start‘ and ‘UID put in receive reset state by RES
command‘.
0100 (EI): Error Indication
EI status indication reports that act bit has been
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detected equal zero.
0110 (UAI): U interface Activation Indication
UAI reports that the line is superframe synchro-
nized.
1000 (AP): Activation Pending
Being in one of the deactivated states, AP reports
that a wake up tone has been detected from the
line. Beeing in the U-only-activated state, AP re-
ports that sai bit has been detected equal one
from the line. Is intended to reflect an activation
attempt at the S/T interface.
1100 (AI): Activation Indication
AI reports that UID is superframe synchronized
with act bit received equal one. TE side of the
loop relative to the UID is active
1111 (DI): Deactivation Indication DI reports that
UID has entered the deactivated state (J1).
B1, B2 and D channels transparency
UID is able to control automatically transparency of
B1, B2 and D channels. Nevertheless, when ETC
bit in CR2 register is set equal 1, transparency is
forced as soon as the line is synchronized.
It is also possible to control each data channel B1,
B2, D enabling at the DSI/GCI interface inde-
pendently by means of bits EB1, EB2 and ED in
CR4 register; Set equal 1, B1, B2 or D channel on
the DSI/GCI interface is enabled; In this case, out
of the transparency state (s), ones are forced on
thee relevant time slot of the DSI/GCI, and ones or
zeros are transmitted on the line conforming T1E1
recommendations. Set equal 0, relevant time slot
on DSI/GCI is always in high impedance state and
ones or zeros are transmitted on the line. In this last
case, as soon as transparency is enabled, ones are
transmitted to the line.
When RDT test command is applied, transpar-
ency on 2B+D is forced. This intend to permit the
user, if required, to send a random sequence of
bits to the line. Please note that the on-chip
scrambler normally ensures transmission of
equiprobable levels to the line, even if logical one
only is provided to the DSI/GCI system interface.
INTERNAL REGISTERS DESCRIPTION.
Here
STLC5411 internal registers.
Internal registers can be accessed:
a) In GCI mode, according to the monitor channel
exchange rules. For RXACT and TXACT also
through C/I channel.
b) in W/DSI mode, using the MICROWIRE inter-
face according to the rules described in section
” W control interface”.
Table 8 gives the list of all the STLC5411 internal
registers can be used in MICROWIRE mode.
Table 9 gives the list of all the STLC5411 internal
registers can be used in GCI mode.
Registers are grouped by types and address ar-
following
a
detailed
description
of