STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 28

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

STLC5411
Table 4: NT-to-Network 2B1Q Superframe Technique and Overhead Bit Assignments.
NT-to-Network superframe delay offset from Network-to-NT superframe by 60
All bits than the Sync Word are scrambled.
Symbols & Abbreviations:
Figure 6: Example of 2B1Q Quaternary Symbols.
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”1”
eoc
SW
ISW inverted synchronization word
s
m
act
Frame
Super
2,3,...
#
1
reserve = reserved bit for future standard; set = 1
embedded operations channel
a = address bit
dm = data/message indicator
i = information (data/message)
synchronization word
sign bit (first) in quat
magnitude bit (second) in quat
activation bit
Quat Positions
Bit Positions
Frame
Basic
#
1
2
3
4
5
6
7
8
Sync Word
FRAMING
1-18
ISW
SW
SW
SW
SW
SW
SW
SW
1-9
10-117
19-234
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
2B+D
eoc
eoc
eoc
eoc
118s
eoc
eoc
eoc
eoc
235
M
1
dm
dm
a1
a1
i3
i6
i3
i6
ps
ps
ntm
cso
crc
febe far end block error bit (set = 0 for errored
sai
1
2
,
power status bits (set = 0 to indicate power
problems)
NT in Test Mode bit (set = 0 to indicate test mode
cold-start-only bit (set = 1 to indicate cold-start-only
cyclic redundancy check: covers 2B+D & M4
1 = most significant bit
2 = next most significant bit
etc
superframe)
S/T interface activation indication bit.
118m
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
236
M
2
a2
a2
i1
i4
i7
i1
i4
i7
Overhead Bits (M
eoc
eoc
119s
eoc
eoc
eoc
eoc
eoc
eoc
237
M
3
a3
a3
i2
i5
i8
i2
i5
i8
119m
238
ntm
ps
ps
cso
act
M
sai
1
1
2 quats (about 0.75 ms).
4
1
2
1-
M
6
)
120s
crc
239
crc
crc
crc
crc
crc
M
1
1
5
11
1
3
5
7
9
120m
crc
crc
febe
crc
crc
crc
crc
240
M
1
6
10
12
2
4
6
8