STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 7

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

PIN FUNCTIONS (specific Micro Wire mode)
Pin
12
13
14
15
16
17
18
19
22
25
26
27
Name
DCLK
CCLK
BCLK
SFSx
LSDb
SFSr
INTb
CO
CS
Dx
Bx
Dr
CI
In/Out
In Out
In Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
Bit clock input or output depending of the CMS bit in CMR register. When
BCLK is an input, its frequency may be any multiple of 8 KHz from 256 KHz
to 4096 KHz in formats 1, 2, 3; 512 KHz to 6176 KHz in format 4. When
BCLK is an output, its frequency is 256 KHz, 512 KHz, 1536 KHz, 2048
KHz or 2560 KHz depending of the selection in CR1 register. In this case,
BCLK is locked to the recovered clock received from the line. Input or
Output BCLK is synchronous with FSa/FSb. Datas are shifted in and out (on
Bx and Br) at the BCLK frequency in formats 1, 2, 3. In format 4 datas are
shifted out at half the BCLK frequency.
2B+D input. Basic access data to transmit to the line is shifted in on the
falling edges (at the BCLK frequency or the half BCLK frequency if format 4
is selected) during the assigned time-slots. When D channel port is
enabled, only B1 & B2 sampled on Bx.
D channel clock output when the D channel port is enabled in continuous
mode. Datas are shifted in and out (on Dx and Dr) at 16 KHz on the falling
and rising edges of DCLK respectively. In master mode, DCLK is
synchronous with BCLK.
D channel data output when the D channel port is enabled. D channel data is
shifted out from the UID on this pin in 2 selectable modes: in TDM mode data
is shifted out at the BCLK frequency (or half BCLK frequency in format 4) on
the ridsing edges when the assigned time slot is active. In continuous mode
data is shifted out at the DCLK frequency on the rising edge continuously.
D channel data input when the D channel port is enabled. D channel data is
shifted in from the UID on this pin in 2 selectable modes: in TDM mode data
is shifted in at the BCLK frequency (or half BCLK frequency in format 4) on
the falling edges when the assigned time slot is active. In continuous mode
data is shifted out at the DCLK frequency on the falling edge continuously.
Clock input for the MICROWIRE control channel: data is shifted in and out on
CI and CO pins with CCLK frequency following 2 modes. For each mode the
CCLK polarity is indifferent. CCLK may be asynchronous with all the others
UID clocks.
MICROWIRE control channel serial input: Two bytes data is shifted out the
UID on this pin on the rising or the falling edge of CCLK depending of the
working mode.
MICROWIRE control channel: serial output: two bytes data is shifted out the
UID on this pin on the rising or the falling edge of CCLK depending of the
working mode. When not enabled by CS low, CO is high impedance.
Tx Super frame synchronization. The rising edge of SFSx indicates the
beginning of the transmit superframe on the line. In NT mode SFSx is always
an output. In LT mode SFSx is an input or an output depending of the SFS bit
in CR2 register. When SFSx is input, it must be synchronous of FSa.
Rx Super frame synchronization. The rising edge of SFSr indicates the
begenning of the received superframe on the line. UID provides this output
only when ESFR bit in CR4 register is to 1.
Line Signal Detect output (default conf.): This pin is an open drain output
which is normally in the high impedance state but pulls low when the device
previously in the power down state receives a wake-up by Tone from the
line. This signal is intended to be used to wake-up a micro-controller from a
low power idle mode. The LSD output goes back in the high impedance
state when the device is powered up.
Interrupt output: Latched open-drain output signal which is normally high
impedance and goes low to request a read cycle. Pending interrupt data is
shifted out from CO at the following read-write cycle. Several pending interrupts
may be queued internally and may provide several interrupt requests. INT is
freed upon receiving of CS low and can goes low again when CS is freed.
Chip Select input: When this pin is pulled low, data can be shifted in and out
from the UID through CI & CO pins. When high, this pin inhibits the
MICROWIRE interface. For normal read or write operation, CS has to be
pulled low for 16 CCLK periods of time.
Description
STLC5411
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