STLC5411 ST Microelectronics, STLC5411 Datasheet - Page 49

• Manufacturer Part Number: STLC5411
• Description: 2B1Q U INTERFACE DEVICE
• Manufacturer: ST Microelectronics

EOC Receive EOC status register read.
When EOC bit is set equal one, UID automatically
loads the current value of RXEOC register in the
interrupt stack independently of any status
change.
M4 Receive M4 overhead bits status register
read.
When M4 bit is set equal one, UID automatically
loads the current value of RXM4 register in the in-
terrupt stack independently of any status change.
M56 Receive M5 and M6 overhead bits status
register read.
When M56 bit is set equal one, UID automatically
loads the current value of RXM56 register in the
interrupt stack independently of any status
change.
ACT Activation indication status.
When ACT bit is set equal one, UID automatically
loads the current value of RXACT register in the
interrupt stack independently of any status
change.
In GCI mode, the RXACT read back always uses
the monitor channel.
STATUS
When STATUS bit is set egal one, UID automat-
ically loads the current value of STATUS register
in the interrupt stack independently of any status
change.
RST
only).
When RST bit is set equal one, UID is fully reset
including configuration registers, state machine
and all coefficients and reset to their default
value. UID enters in the power-down state.
Transmit EOC register (TXEOC)
After reset: FFFH
TXEOC Register is constituted of 12 bits, 3 bits
XEOC1 XEOC2
RESET (MICROWIRE/DSI
XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8
configuration
address (EFG), 1 bit data/message Flag (H), 8
bits information (XEOC1 - XEOC8). When trans-
mitting SL2/SL3 or SN3 signal. STLC5411 shall
continuously send into the EOC channel field the
eoc bits twice per superframe. TXEOC register is
loaded in the transmit register at each half a su-
perframe.
The address of this register is composed only of 4
bits. Read-back can be performed by means of a
read-back command 6100H.
Receive EOC register (RXEOC)
(read only)
After reset: FFFH
The RX EOC Register is constituted of 12 bits.
When the line is fully activated (super frame syn-
chronized) and when a new eoc message is re-
ceived and validated in accordance with the crite-
ria selected in the Configuration Register OPR,
the RX EOC Register is queued in the interrupt
register stack. The address of this register is com-
posed only of 4 bits.
It is always possible to read this register by writ-
ing RXEOC = 1 in RXOH register
Identification Register (IDR)
Fixed value: 08H
(read only)
When a read-back operation of IDR register is en-
tered, UID loads the Identification Register in the
interrupt stack. This register provides a reserved
identification code agreed by GCI standard: 08H.
IDR register is accessible via two addresses.
MWPS Micro Wire Port Select register (Signifi-
cant in microwire mode only).
(write only)
Default value: Mode A (5410 compatible)
Note: Soft Reset has no effect on the select
mode.
REOC1 REOC2 REOC3 REOC4 REOC5 REOC6 REOC7 REOC8
– Writting FFH value select the mode B to ex-
– Writing 00H value select the mode A (See Mi-
change data onto CI & CO
crowire control interface paragraph for more
details Mode A, Mode B).
STLC5411
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