Z8S180 Zilog., Z8S180 Datasheet - Page 126

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

2. Specify memory
3. Load the number of bytes to transfer in BCR0
4. The DMA request sense mode (DMS0 bit in DCNTL) must be
5. Enable or disable DMA termination interrupt with the DIE0 bit in
6. Program DE0 =
The ASCI receiver or transmitter using DMA is initialized to allow the
first DMA transfer to begin.
The ASCI receiver must be empty as shown by RDRF =
The ASCI transmitter must be full as shown by TDRE = 0. Thus, the first
byte is written to the ASCI Transmit Data Register under program
control. The remaining bytes are transferred using DMA.
Channel 1 DMA
DMAC Channel 1 performs memory to/from I/O transfers. Except for
different registers and status/control bits, operation is exactly the same as
described for channel 0 memory to/from I/O DMA.
To initiate a DMA channel 1 memory to/from I/O transfer, perform the
following operations:
1. Load the memory address (20 bits) into MAR1.
2. Load the I/O address (16 bits) into IAR1.
3. Program the source/destination and address increment/decrement
decrement in the SM0, SM1, DM0 and DM1 bits of DMODE.
specified as edge sense.
DSTAT.
the DMA operation with the ASCI begins under control of the ASCI
generated internal DMA request.
mode using the DIM1 and DIM0 bits in DCNTL.
1
(with DWE0 =
I/O transfer mode and address increment/
0
in the same access) in DSTAT and
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
0
.
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