Z8S180 Zilog., Z8S180 Datasheet - Page 98

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

Interrupt Sources During RESET
Interrupt Vector Register (I)
All bits are reset to
logical address
and internal interrupts) overlap with fixed restart interrupts like RESET
(0), NMI (
vector table(s) are built elsewhere in memory and located on 256 byte
boundaries by reprogramming I with the LD I, A instruction.
IL Register
Bits 7 - 5 are reset to
The IL Register can be programmed to locate the vector table for INT1,
INT2 and internal interrupts on 32-byte subboundaries within the 256
byte area specified by I.
IEF1, IEF2 Flags
Reset to
ITC Register
ITE0 set to 1. ITE1, ITE2 reset to
instruction, which sets IEF1 to
that the ITE1 and ITE2 bits be respectively set to
I/O Control Registers
Interrupt enable bits reset to
CSI/O, ASCI) interrupts are disabled and can be individually enabled by
writing to each I/O control register interrupt enable bit.
0
. Interrupts other than NMI and TRAP are disabled.
0066H
0000H
), INT0 Mode 1 (
0
. Because I =
0
vectored interrupts (INT0 Mode 2, INT1, INT2,
0
. All Z8X180 on-chip I/O (PRT, DMAC,
1
. Enabling INT1 and INT2 also requires
0038H
0
0
. INT0 can be enabled by the EI
locates the vector tables starting at
) and RST (
1
M PU Us e r M anual
by writing to ITC.
UM005001-ZMP0400
0000H
Z 8018x Fam il y
-
0038H
). The
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