APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 16
![no-image](/images/no-image-200.jpg)
APA075-BGB
Manufacturer Part Number
APA075-BGB
Description
ProASIC Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.APA075-BGB.pdf
(174 pages)
- Current page: 16 of 174
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Power-Up Sequencing
While ProASIC
of V
start-up. V
V
guidelines may result in undesirable pin behavior during
system start-up. For more information, refer to Actel’s
Power-Up Behavior of ProASIC
note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASIC
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an input buffer (containing a
Figure 1-10 • Recommended Termination for LVPECL Inputs
Figure 1-11 • LVPECL High and Low Threshold Values
Table 1-5 •
1 -1 0
Symbol
V
V
V
DDP
IH
IL
ID
ProASIC
DD
on ProASIC
and V
PLUS
PLUS
DD
LVPECL Receiver Specifications
devices have a single LVPECL input pad on
should be powered up simultaneously with
DDP
Flash Family FPGAs
PLUS
PLUS
power-up is important during system
devices are live at power-up, the order
From LVPECL Driver
devices. Failure to follow these
Input High Voltage
Input Low Voltage
Differential Input Voltage
NPECL
PPECL
PLUS
Voltage
2.125
Devices
2.72
1.49
0.86
Parameter
Z = 50 Ω
Z = 50 Ω
0
0
application
v5.7
R = 100 Ω
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from V
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull ups. Recommended termination for
LVPECL inputs is shown in
cell compares voltages on the PPECL (I/P) pad (as
illustrated in
the results to the global MUX
This high-speed, low-skew output essentially controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels
Min.
1.49
0.86
0.3
Figure
+
_
(Table
1-11) and the NPECL pad and sends
1-5).
2.125
Max
2.72
V
DD
Figure
(Figure 1-14 on page
Data
DD
1-10. The LVPECL pad
only.
Units
V
V
V
1-14).
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