APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 78

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

FIFO Reset
Notes:
1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.
2. The plot shows the normal operation status.
Figure 1-48 • FIFO Reset
Table 1-66 • T
1 -7 2
Symbol t
CBRSH
CBRSS
ERSA
FRSA
RSL
THRSA
WBRSH
WBRSS
Notes:
1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
2. All –F speed grade devices are 20% slower than the standard numbers.
ProASIC
1
1
1
1
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
WCLKS or RCLKS ↑ hold from RESETB ↑
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
WB ↑ setup to RESETB ↑
WCLKS, RCLKS
EQTH, GETH
t ERSA , t FRSA
WRB/RBD
RESETB
DD
EMPTY
Description
t THRSA
FULL
DD
= 2.3 V to 2.7 V for Commercial/industrial
1
1
= 2.3 V to 2.7 V for Military/MIL-STD-883
t CBRSS
t RSL
v5.7
Min.
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
Max.
t WBRSS
Units
ns
ns
ns
ns
ns
ns
ns
ns
t WBRSH
Cycle Start
Cycle Start
t CBRSH
Synchronous mode only
Synchronous mode only
Asynchronous mode only
Asynchronous mode only
Notes