APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 21

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.
Figure 1-15 • Input Connectors to ProASIC
Table 1-7 •
MUX
FBSEL
1
2
3
XDLYSEL
0
1
OBMUX
0
1
2
4
5
6
7
OAMUX
0
1
2
3
Clock-Conditioning Circuitry MUX Settings
Package Pins
Internal Feedback
Internal Feedback and Advance Clock Using FBDLY
External Feedback (EXTFB)
Feedback Unchanged
Deskew feedback by advancing clock by system delay
Primary bypass, no divider
Primary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
Reserved
Phase Shift Clock by +180°
Reserved
Secondary bypass, no divider
Secondary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
NPECL
PPECL
GLMX
GL
GL
Legend
PECL Pad Cell
Physical I/O
Std. Pad Cell
Std. Pad Cell
Std. Pad Cell
Physical Pin
DATA Signals to the Core
DATA Signals to the PLL Block
Buffers
Datapath
PLUS
GLA
GLB
Clock Conditioning Circuitry
CORE
v5.7
DATA Signals to the Global MUX
Control Signals to the Global MUX
Configuration Tile
Configuration Tile
–0.25 to –4 ns in 0.25 ns increments
Fixed delay of -2.95 ns
+0.25 to +4 ns in 0.25 ns increments
+0.25 to +4 ns in 0.25 ns increments
Global MUX
ProASIC
Comments
Global MUX B
OUT
External
Feedback
Global MUX A
OUT
PLUS
Flash Family FPGAs
1-15