APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 77

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Synchronous FIFO Write
Note: The plot shows the normal operation status.
Figure 1-47 • Synchronous FIFO Write
Table 1-65 • T
Symbol t
CCYC
CMH
CML
DCH
DCS
FCBA
ECBA
ECBH,
FCBH,
HCBH
HCBA
WPCA
WPCH
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑
WRCS, WBCS
Notes:
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. All –F speed grade devices are 20% slower than the standard numbers.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Clock high phase
Clock low phase
DI hold from WCLKS ↑
DI setup to WCLKS ↑
Old EMPTY, FULL, EQTH, & GETH valid hold
time from WCLKS ↓
Old WPE valid from WCLKS ↑
WRB & WBLKB setup to WCLKS ↑
Cycle time
New FULL access from WCLKS ↓
EMPTY↓ access from WCLKS ↓
EQTH or GETH access from WCLKS ↓
New WPE access from WCLKS ↑
Description
t WRCH , t WBCH
EQTH, GETH
t WRCS , t WBCS
WRB, WBLKB
DD
WCLKS
DD
EMPTY
= 2.3 V to 2.7 V for Commercial/industrial
FULL
WPE
= 2.3 V to 2.7 V for Military/MIL-STD-883
t DCS
DI
t WPCH
t DCH
Cycle Start
t WPCA
t CMH
Min.
3.0
3.0
7.5
3.0
3.0
0.5
1.0
4.5
3.0
0.5
1.0
v5.7
t CCYC
1
1
Max.
t HCBA
1.0
0.5
t CML
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t HCBH
t ECBH , t FCBH
t ECBA , t FCBA
(Full Inhibits Write)
Empty/full/thresh are invalid from the end of
hold until the new access is complete
WPE is invalid, while PARGEN is active
ProASIC
PLUS
Notes
Flash Family FPGAs
1-71